1) Field of the Invention
The present invention relates to a technology for supporting verification in which a logic design of hardware is verified using a logic simulation.
2) Description of the Related Art
Conventionally, two major types of verification coverage are used as an index of sufficiency of logic simulation patterns. One of the two types of verification coverage is functional coverage, which is to check whether all functions of a verification target are covered based on external specifications of the verification target.
The other one is code coverage, which is based on a source code of a verification target. The code coverage includes, for example, line coverage, toggle coverage, and finite-state-machine (FSM) coverage. The line coverage is aimed at executing all lines in the source code. The toggle coverage is aimed at changing all signal lines described in the source code. The FSM coverage aimed at covering all states and state transitions by determining a FSM from the source code.
The functional coverage and the code coverage have conventionally been used. An example of a conventional technology using the functional coverage is a coverage calculating method disclosed in Japanese Patent Laid-Open Publication No. 2004-70457. In this coverage calculating method, a property and test patterns actually executed are input, and based on the property, a coverage rate of effective test patterns corresponding to the property is calculated.
An example of a method of measuring the functional coverage is a calculating method disclosed in Japanese Patent Laid-Open Publication No. H3-062172. In this method, the functional coverage is set to 100 percent (%) in a logic simulation, thereby verifying whether all functions required as seen from outside are accurately implemented.
An example of a conventional technology using the code coverage is a coverage scheme disclosed in Japanese Patent Laid-Open Publication No. S63-205760. In this coverage scheme, information regarding signal variations in a logic simulation is recorded so as to operate all signals.
However, in the functional coverage described above, even a case in which no distinction can be seen from the outside may be fragmented into sub-cases for processing in actual implementation in an internal hardware. All of these sub-cases should be covered, but the functional coverage only covers one of these sub-cases. Therefore, verification is disadvantageously insufficient.
For example, a logic circuit is assumed to have external specifications as follows:
(1) The circuit includes five input terminals A, B, C, D, and E and one output terminal F;
(2) The circuit has a first function such that, when a value of A is 0, a logical function f1 is applied to two input values of B and C to obtain a result f1 (B, C) for output to F; and
(3) The circuit has a second function such that, when the value of A is 1, a logical function f2 is applied to two input values of D and E to obtain a result f2 (D, E) for output to F.
From these external specifications, as the functional coverage, a requirement of “a pattern of executing the first function and a pattern of executing the second function are executed more than once for each the patterns” is considered. For this requirement, 100% coverage is achieved with simulations that are performed regarding only two patterns, executing the first function (A, B, C, D, E)=(0, 0, 0, 0, 0) and executing the second function (A, B, C, D, E)=(1, 0, 0, 0, 0).
This is a minimum coverage requirement to be achieved, but is hardly sufficient. For example, requirement that is further subdivided may include “the pattern of executing the first function is executed on all combinations of the values of B and C, and the pattern of executing the second function is executed on all combinations of the values of D and E”. However, in an actual large-scale logic circuit (having internal states and including many input terminals), such a way of executing the patterns on all combinations is unrealistic. Therefore, the coverage requirement should be moderate.
On the other hand, if the code coverage is set to 100%, execution of the source code can be roughly checked. However, to make verification meaningful, execution at a stage where the execution may influence the final result is required instead of merely executing. In view of the above, such a requirement has not been included in the conventional code coverage.
FIG. 22 is a circuit diagram of the logic circuit described above. For example, the toggle coverage, which is one type of the code coverage, is applied to a logic circuit 2200 shown in FIG. 22. In toggle coverage, calculation is performed based on whether a value variation occurs in each of signal lines in the circuit during simulation. In this example, because 10 signal lines A to J are present, a modulus of the coverage is 10.
When simulation is carried out with two patterns (0, 0, 0, 0, 0) and (1, 0, 0, 0, 0) causing 100% functional coverage, simulation results shown in FIGS. 23 and 24 are obtained. FIGS. 23 and 24 are schematics for explaining the simulation results of the logic circuit 2200. In the simulation results shown in FIGS. 23 and 24, three signal lines A, H, and F have variations in value. Therefore, only 30% of the toggle coverage is achieved. Then, a pattern (1, 1, 1, 1, 1) is added for the simulation, a simulation result shown in FIG. 25 is obtained. FIG. 25 is a schematic for explaining the simulation result of the logic circuit 2200. As shown in FIG. 25, rests of the signal lines also have variations in value, and 100% toggle coverage is achieved.
However, the logic circuit 2200 has a structure in which, where A=1, the values of B, C, and G do not influence on an output F. Therefore, value variations of B, C, and G covered by the pattern (1, 1, 1, 1, 1) finally added does not serve a purpose of verification. As such, by merely attempting to achieve the functional coverage or the code coverage individually, omission in verification as described above cannot be prevented.
On the other hand, when all combinations of the functional coverage and the code coverage are simply tried to be covered, there might be a combination theoretically unachievable among the combinations. Therefore, it is impossible to determine to what extent the combinations should be covered to be sufficient for verification. Therefore, the combinations of the functional coverage and the code coverage are also impractical.
For example, in the example described above, the modulus of the functional coverage is 2, and the modulus of the toggle coverage is 10. Therefore, 20 combinations are considered. However, in practice, A is always 0 when the first function is executed, and therefore, a combination of execution for the first function and a value variation in the signal A is not achievable. Moreover, the value of the signal line I is fixed to 0 due to A=0. Therefore, a combination of execution of the first function and a value variation in the signal line I is not achievable either. Similarly, neither a combination of the first function and a value variation in the signal line J nor a combination of the second function and value variations in the signal lines A and H are achievable. To an actual large-scale circuit, performing verification individually on each combination is difficult and impractical.